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| low dropout linear voltage regulator TLS820D0 TLS820D0elv50 TLS820D0elv33 linear voltage regulator automotive power data sheet rev. 1.0, 2016-02-08
data sheet 2 rev. 1.0, 2016-02-08 TLS820D0 table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 pin assignment TLS820D0elv50 and TLS820D0elv33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 pin definitions and functions TLS820D0elv50 and tls820d 0elv33 . . . . . . . . . . . . . . . . . . . . . . . 6 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 block description and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 typical performance characteristics voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 5.3 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 typical performance characteristics current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 typical performance characteristics enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.8 typical performance characteristics reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 selection of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2.1 input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2.2 output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.5 further application informat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table of contents data sheet 3 rev. 1.0, 2016-02-08 low dropout linear voltage regulator TLS820D0 1overview features ? wide input voltage range from 3.0 v to 40 v ? fixed output voltage 5 v or 3.3 v ? output voltage precision 2 % ? output current capability up to 200 ma ? ultra low current consumption typ. 40 a ? very low dropout voltage typ. 70 mv @100 ma ? stable with ceramic output capacitor of 1 f ? delayed reset at power-on with 2 programmable delay times 8.5 ms / 16.5 ms ? adjustable reset threshold down to 2.50 v ? enable, undervoltage rese t, overtemperature shutdown ? output current limitation ? wide temperature range ? green product (rohs compliant) ? aec qualified figure 1 pg-ssop-14 TLS820D0 overview data sheet 4 rev. 1.0, 2016-02-08 functional description the TLS820D0 is a high performance very low dropout linear voltage regulator for 5 v (TLS820D0v50) or 3.3 v (TLS820D0v33) supply in a pg-ssop-14 package. with an input voltage range of 3 v to 40 v and very low quiescent of only 40 a, these regulators are perfectly suitable for automotive or any other supply system s connected to the battery permanently. the TLS820D0 provides an output voltage accuracy of 2 % and a maximum output current up to 200 ma. the new loop concept combines fast regulation and very good stability while requiring only one small ceramic capacitor of 1 f at the output. at cu rrents below 100 ma the device will ha ve a very low typical dropout voltage of only 70 mv (for 5 v device) and 80 mv (for 3.3 v device). the operating range starts already at input voltages of only 3 v (extended operating range). this makes the TLS820D0 also suitable to supply automotive systems that need to operate during cranking condition. the device can be switched on and off by the enable feature as described in chapter 5.5 . the output voltage is supervised by the reset feature, including undervoltage reset, delayed reset at power-on and an adjustable lower reset threshold, more details can be found in chapter 5.7 . internal protection features like output current limitation and overtemperature shutdown are implemented to protect the device against immediate damage due to failu res like output short circuit to gnd, over-current and over-temperatures. choosing external components an input capacitor c i is recommended to compensate line influences. the output capacitor c q is necessary for the stability of the regulating circuit. TLS820D0 is designed to be also st able with low esr ceramic capacitors. type package marking TLS820D0elv50 pg-ssop-14 820d0v50 TLS820D0elv33 pg-ssop-14 820d0v33 TLS820D0 block diagram data sheet 5 rev. 1.0, 2016-02-08 2 block diagram figure 2 block diagram TLS820D0elv50 and TLS820D0elv33 bandgap reference gnd q i temperature shutdown en enable reset ro radj dt current limitation data sheet 6 rev. 1.0, 2016-02-08 TLS820D0 pin configuration 3 pin configuration 3.1 pin assignment tls820d 0elv50 and TLS820D0elv33 figure 3 pin configuration 3.2 pin definitions and functi ons TLS820D0elv50 and TLS820D0elv33 pin symbol function 1i input it is recommended to place a small ceramic capacitor (e.g. 100 nf) to gnd, close to the ic terminals, in order to compensate line influences. see also chapter 6.2.1 2, 4, 6, 7 n.c. not connected leave open or connect to gnd 3en enable (integrated pull-down resistor) enable the ic with high level input signal; disable the ic with low level input signal; 5gnd ground 8radj reset threshold adjustment connect to gnd to use standard value; connect an external voltage divi der to adjust reset threshold 9dt delay timing (integrated pull-down resistor) connect to gnd or q to select reset timing acc. to table 8 11 ro reset output (integrated pull-up resistor to q) open collector output; leave open if the reset function is not needed 10, 12, 13 n.c. not connected leave open or connect to gnd 14 q output voltage connect output capacitor c q to gnd close to the ic?s terminals, respecting the values specified for its capacitance and esr in ?functional range? on page 8 pad ? exposed pad connect to heatsink area; connect to gnd i n.c. n.c. gnd q n.c. n.c. ro dt radj 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ssop-14 en n.c. n.c. n.c. TLS820D0 general product characteristics data sheet 7 rev. 1.0, 2016-02-08 4 general product characteristics 4.1 absolute maximum ratings note: 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. table 1 absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground (unless otherwise specified) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. input i, enable en voltage v i , v en -0.3 ? 45 v ? p_4.1.1 output q, reset output ro voltage v q , v ro -0.3 ? 7 v ? p_4.1.3 delay timing dt, reset threshold adjustment radj voltage v dt , v radj -0.3 ? 7 v ? p_4.1.6 temperatures junction temperature t j -40 ? 150 c ? p_4.1.7 storage temperature t stg -55 ? 150 c ? p_4.1.8 esd absorption esd susceptibility to gnd v esd -2 ? 2 kv 2) hbm 2) esd susceptibility, hbm accordin g to ansi/esda/jedec js001 (1.5 k ? , 100 pf) p_4.1.9 esd susceptibility to gnd v esd -500 ? 500 v 3) cdm 3) esd susceptibility, charged device model ?cdm? according jedec jesd22-c101 p_4.1.10 esd susceptibility pin 1, 7, 8, 14 (corner pins) to gnd v esd1,7,8,14 -750 ? 750 v 3) cdm p_4.1.11 data sheet 8 rev. 1.0, 2016-02-08 TLS820D0 general product characteristics 4.2 functional range note: within the functional or operating range, the ic operat es as described in the circuit description. the electrical characteristics are specif ied within the conditions given in th e electrical char acteristics table. table 2 functional range t j = -40 c to +150 c; all voltages with respect to ground (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. input voltage range v i v q,nom + v dr ?40v 1) ? 1) output current is limited internaly an d depends on the input voltage, see electrical characteristics for more details. p_4.2.1 extended input voltage range v i,ext 3.0 ? 40 v 2) ? 2) when v i is between v i,ext,min and v q,nom + v dr , v q = v i - v dr . when v i is below v i,ext,min , v q can drop down to 0 v. p_4.2.3 enable voltage range v en 0?40v? p_4.2.5 output capacitor?s requirements for stability c q 1??f 3)4) ? 3) not subject to production test, specified by design. 4) the minimum output capacitance requ irement is applicable for a worst case capacitance tolerance of 30% p_4.2.6 esr esr(c q ) ??100 ? 3) ? p_4.2.7 junction temperature t j -40 ? 150 c ? p_4.2.9 TLS820D0 general product characteristics data sheet 9 rev. 1.0, 2016-02-08 4.3 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . table 3 thermal resistance parameter symbol values unit note / test condition number min. typ. max. package version pg-ssop-14 junction to case r thjc ?9 ? k/w 1) ? 1) not subject to production test, specified by design p_4.3.1 junction to ambient r thja ?43? k/w 1)2) 2s2p board 2) specified r thja value is according to jedec jesd51-2,-5,-7 at na tural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. p_4.3.2 junction to ambient r thja ?128? k/w 1)3) 1s0p board, footprint only 3) specified r thja value is according to jedec jesd 51-3 at natural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 114.3 1.5 mm 3 board with 1 copper layer (1 x 70m cu). p_4.3.3 junction to ambient r thja ?58? k/w 1)3) 1s0p board, 300 mm 2 heatsink area on pcb p_4.3.4 junction to ambient r thja ?50? k/w 1)3) 1s0p board, 600 mm 2 heatsink area on pcb p_4.3.5 data sheet 10 rev. 1.0, 2016-02-08 TLS820D0 block description and electrical characteristics 5 block description and el ectrical characteristics 5.1 voltage regulation the output voltage v q is divided by a resistor network. this fracti onal voltage is compared to an internal voltage reference and the pass transistor is driven accordingly. the control loop stability depen ds on the output capacitor c q , the load current, the chip temperature and the internal circuit design. to ensure stable operation, the output capacitor?s capacitance and its equivalent series resistor (esr) requirements given in ?functional range? on page 8 have to be maintained. for details, also see the typical performance graph ?output capacitor series resistor esr(cq) versus output current iq? on page 15 . as the output capacitor also has to buffer load st eps, it should be sized according to the application?s needs. an input capacitor c i is recommended to compensate line influences. in order to block influences like pulses and hf distortion at input side, an additional reverse polarity protection diode and a combination of several capacitors for filtering should be used. connect the c apacitors close to the component?s terminals. in order to prevent overshoots during start-up, a smooth ramp up function is implemented. this ensures almost no output voltage overshoots during start-up, most ly independent from load and output capacitance. whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is limited and the output voltage decreases. the overtemperature shutdown circuit prevents the ic from immediate destruction under fault conditions (e.g. output continuously short-circuit) by switching off the power stage. after the chip has cooled down, the regulator restarts. this leads to an oscillatory behavior of the output volt age until the fault is re moved. however, junction temperatures above 150 c are outside the maximum rating s and therefore significantly reduce the ic?s lifetime. figure 4 voltage regulation figure 5 output voltage vs. input voltage load supply c i regulated output voltage i q i i bandgap reference gnd q i temperature shutdown en enable reset ro radj dt c esr c q v i v q current limitation v t v q,nom v i v dr v q v i,ext,min TLS820D0 block description and electrical characteristics data sheet 11 rev. 1.0, 2016-02-08 table 4 electrical characteristics voltage regulator 5 v version t j = -40 c to +150 c, v i = 13.5 v, all voltages with respect to ground (unless otherwise specified) typical values are given at t j = 25 c parameter symbol values unit note / test condition number min. typ. max. output voltage precision v q 4.9 5.0 5.1 v 0.05 ma < i q <200ma 5.44 v < v i < 28v p_5.1.1 output voltage precision v q 4.9 5.0 5.1 v 0.05 ma < i q <100ma 5.27 v < v i <40v p_5.1.2 output voltage start-up slew rate d v q /dt 3.0 7.5 18 v/ms v i >18v/ms c q =1f 0.5 v < v q <4.5v p_5.1.7 output current limitation i q,max 201 350 550 ma 0 v < v q <4.8v p_5.1.8 load regulation steady-state ? v q,load -15 -1.5 5 mv i q = 0.05 ma to 200 ma v i = 6 v p_5.1.10 line regulation steady-state ? v q,line -20 0 20 mv v i = 8 v to 32 v i q =1ma p_5.1.12 dropout voltage v dr = v i - v q v dr ? 140 340 mv 1) i q = 200 ma 1) measured when the output voltage v q has dropped 100 mv from the nominal value obtained at v i = 13.5v p_5.1.14 dropout voltage v dr = v i - v q v dr ?70170mv 1) i q = 100 ma p_5.1.15 power supply ripple rejection psrr ?59?db 2) f ripple = 100 hz v ripple = 0.5 vpp 2) not subject to production test, specified by design p_5.1.18 overtemperature shutdown threshold t j,sd 151 ? 200 c 2) t j increasing p_5.1.19 overtemperature shutdown threshold hysteresis t j,sdh ?15?k 2) t j decreasing p_5.1.20 data sheet 12 rev. 1.0, 2016-02-08 TLS820D0 block description and electrical characteristics table 5 electrical characteristics voltage regulator 3.3 v version t j = -40 c to +150 c, v i = 13.5 v, all voltages with respect to ground (unless otherwise specified) typical values are given at t j = 25 c parameter symbol values unit note / test condition number min. typ. max. output voltage precision v q 3.23 3.3 3.37 v 0.05 ma < i q <200ma 3.72 v < v i <28v p_5.1.21 output voltage precision v q 3.23 3.3 3.37 v 0.05 ma < i q <100ma 3.55 v < v i <40v p_5.1.22 output voltage start-up slew rate d v q /dt 3.0 7.5 18 v/ms v i >18v/ms c q =1f 0.33 v < v q <2.97v p_5.1.27 output current limitation i q,max 201 350 550 ma 0 v < v q <3.1v p_5.1.28 load regulation steady-state ? v q,load -15 -1.5 5 mv i q = 0.05 ma to 200 ma v i =6v p_5.1.30 line regulation steady-state ? v q,line -15 0 15 mv v i = 8 v to 32 v i q =1ma p_5.1.32 dropout voltage v dr = v i - v q v dr ? 160 350 mv 1) i q = 200 ma 1) measured when the output voltage v q has dropped 100 mv from the nominal value obtained at v i = 13.5v p_5.1.34 dropout voltage v dr = v i - v q v dr ?80175mv 1) i q = 100 ma p_5.1.35 power supply ripple rejection psrr ?63?db 2) f ripple = 100 hz v ripple = 0.5 vpp 2) not subject to production test, specified by design p_5.1.38 overtemperature shutdown threshold t j,sd 151 ? 200 c 2) t j increasing p_5.1.39 overtemperature shutdown threshold hysteresis t j,sdh ?15?k 2) t j decreasing p_5.1.40 TLS820D0 block description and electrical characteristics data sheet 13 rev. 1.0, 2016-02-08 5.2 typical performance characteristics voltage regulator typical performanc e characteristics output voltage v q versus junction temperature t j (3.3 v version) output voltage v q versus junction temperature t j (5 v version) dropout voltage v dr versus junction temperature t j (3.3 v version) dropout voltage v dr versus junction temperature t j (5 v version) 0 50 100 150 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 t j [ c] v q [v] i q = 100ma 0 50 100 150 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 t j [ c] v q [v] i q = 100ma 0 50 100 150 0 50 100 150 200 250 300 t j [ c] v dr [mv] i q = 100 ma i q = 200 ma v q = 3.3 v 0 50 100 150 0 50 100 150 200 250 300 t j [ c] v dr [mv] i q = 100 ma i q = 200 ma v q = 5 v data sheet 14 rev. 1.0, 2016-02-08 TLS820D0 block description and electrical characteristics load regulation ? v q,load versus output current change i q line regulation ? v q,line versus input voltage v i output voltage v q versus input voltage v i (3.3 v version) output voltage v q versus input voltage v i (5 v version) 0 50 100 150 200 ?5 ?4.5 ?4 ?3.5 ?3 ?2.5 ?2 ?1.5 ?1 ?0.5 0 i q [ma] v q,load [mv] t j = ?40 c t j = 25 c t j = 150 c v i = 6 v 10 15 20 25 30 ?8 ?6 ?4 ?2 0 2 4 6 8 v i [v] v q,line [mv] t j = ?40 c t j = 25 c t j = 150 c i q = 1 ma 0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 3 3.5 4 v i [v] v q [v] t j = ?40 c t j = 25 c t j = 150 c i q = 100 ma 0 1 2 3 4 5 6 0 1 2 3 4 5 6 v i [v] v q [v] t j = ?40 c t j = 25 c t j = 150 c i q = 100 ma TLS820D0 block description and electrical characteristics data sheet 15 rev. 1.0, 2016-02-08 power supply ripple rejection psrr versus ripple frequency f output capacitor series resistor esr ( c q ) versus output current i q maximum output current i q versus input voltage v i dropout voltage v dr versus output current i q v q = 3.3 v v q = 5 v 10 ?2 10 ?1 10 0 10 1 10 2 10 3 0 10 20 30 40 50 60 70 80 f [khz] psrr [db] i q = 10 ma c q = 1 f v ripple = 0.5 v pp t j = 25 c t j = 25 c c q = 1 f 0.05 1 10 200 10 ?2 10 ?1 10 0 10 1 10 2 10 3 i q [ma] esr(c q ) [ ] stable region unstable region 0 10 20 30 40 0 100 200 300 400 500 600 700 800 v i [v] i q,max [ma] t j = ?40 c t j = 25 c t j = 150 c v q = 0 v 0 50 100 150 200 0 50 100 150 200 250 300 i q [ma] v dr [mv] v q = 3.3 v v q = 5 v t j = 25 c data sheet 16 rev. 1.0, 2016-02-08 TLS820D0 block description and electrical characteristics 5.3 current consumption table 6 electrical characteristics current consumption t j = -40 c to +150 c, v i = 13.5 v (unless otherwise specified) typical values are given at t j = 25 c conditions of other pins: dt = gnd parameter symbol values unit note / test condition number min. typ. max. current consumption i q = i i i q,off ?1.35a v en =0v; t j <105c p_5.3.1 current consumption i q = i i i q,off ??8a v en =0.4v; t j < 125 c p_5.3.3 current consumption i q = i i - i q i q ?4052a i q =0.05ma t j =25c p_5.3.4 current consumption i q = i i - i q i q ?6277a i q =0.05ma t j <125c p_5.3.7 current consumption i q = i i - i q i q ?6280a 1) i q =200ma t j <125c 1) not subject to production test, specified by design p_5.3.9 TLS820D0 block description and electrical characteristics data sheet 17 rev. 1.0, 2016-02-08 5.4 typical performance charac teristics current consumption typical performanc e characteristics current consumption i q versus output current i q current consumption i q versus input voltage v i 0 50 100 150 200 0 10 20 30 40 50 60 70 80 90 100 i q [ma] i q [ua] t j = 25 c 5 10 15 20 25 30 35 40 0 20 40 60 80 100 120 140 160 180 200 v i [v] i q [ua] t j = ?40 c t j = 25 c t j = 150 c v en = 5 v i q = 50 ua data sheet 18 rev. 1.0, 2016-02-08 TLS820D0 block description and electrical characteristics 5.5 enable the TLS820D0 can be switched on and off by the enable feature: connect a high level as specified below (e.g. the battery voltage) to pin en to en able the device; connect a low level as specified below (e.g. gnd) to shut it down. the enable has a built in hysteres is to avoid toggling between on/off stat e, if signals with slow slopes are applied to the en input. table 7 electrical characteristics enable t j = -40 c to +150 c, v i = 13.5 v, all voltages with respect to ground (unless otherwise specified) typical values are given at t j = 25 c parameter symbol values unit note / test condition number min. typ. max. high level input voltage v en,h 2??v v q settled p_5.5.1 low level input voltage v en,l ??0.8v v q 0.1 v p_5.5.2 enable threshold hysteresis v en,hy 100??mv? p_5.5.3 high level input current i en,h ??3.5a v en =3.3v p_5.5.4 high level input current i en,h ??22a v en 18 v p_5.5.6 enable internal pull-down resistor r en 0.95 1.5 2.6 m ? ? p_5.5.7 TLS820D0 block description and electrical characteristics data sheet 19 rev. 1.0, 2016-02-08 5.6 typical performance characteristics enable typical performanc e characteristics input current i in versus input voltage v in (condition: v en = 0 v) enabled input current i en versus enabled input voltage v en output voltage v q versus time (en switched on, 5 v version) output voltage v q versus time (en switched on, 3.3 v version) 0 10 20 30 40 0 5 10 15 20 25 30 v in [v] i in [ua] t j = ?40 c t j = 25 c t j = 150 c v en = 0v 0 10 20 30 40 0 5 10 15 20 25 30 35 40 45 50 v en [v] i en [ua] t j = ?40 c t j = 25 c t j = 150 c 0 500 1000 1500 2000 0 1 2 3 4 5 6 t [us] v q , v en [v] t j = ?40 c t j = 25 c t j = 150 c v en i q = 100 ma 0 500 1000 1500 2000 0 1 2 3 4 5 6 t [us] v q , v en [v] t j = ?40 c t j = 25 c t j = 150 c v en i q = 100 ma data sheet 20 rev. 1.0, 2016-02-08 TLS820D0 block description and electrical characteristics 5.7 reset the TLS820D0?s output voltage is su pervised by the reset feature, includ ing undervoltage re set, delayed reset at power-on and an adjustable reset threshold. the undervoltage reset function sets the pin ro to low, in case v q is falling for any re ason below the reset threshold v rt,low . when the regulator is powered on, the pin ro is held at low for the duration of the power-on reset delay time t rd . figure 6 block diagram reset circuit reset delay time the pin dt is used to set the desired reset delay time t rd . connect this pin either to gnd or q to select the timing according to table 8 . power-on reset delay time the power-on reset delay time is defined by the parameter t rd and allows a microcontro ller and oscillator to start up. this delay time is the time period from exceeding the upper reset switching threshold v rt,high until the reset is released by switching the reset out put ?ro? from ?low? to ?high?. undervoltage reset delay time unlike the power-on reset delay time, the undervoltage reset delay time is defined by the parameter t rd and considers an output undervoltage event where the output voltage v q trigger the v rt,low threshold. reset blanking time the reset blanking time t rr,blank avoids that short undervoltage spikes trigger an unwanted reset ?low? signal. table 8 reset delaytime selection dt connected to t rd gnd 16.5 ms q 8.5 ms gnd q i or supply ro radj control reset optional optional c q vdd micro- controller gnd r adj,1 r adj,2 r ro,int i ro i radj timer s r q or reference dt TLS820D0 block description and electrical characteristics data sheet 21 rev. 1.0, 2016-02-08 reset reaction time in case the output voltage of the regulator drops below the output undervoltage lower reset threshold v rt,low , the reset output ?ro? is set to low, after the delay of the internal reset reaction time t rr,int . the reset blanking time t rr,blank is part of the reset reaction time t rr,int . reset output ?ro? the reset output ?ro? is an open collector output with an integrated pull-up resistor. in case a lower-ohmic ?ro? signal is desired, an external pull-up resistor can be connected to the output ?q?. since the maximum ?ro? sink current is limited, the mi nimum value of the option al external resistor ? r ro,ext ? is given in table ?reset output ro? on page 23 . reset output ?ro? low for vq 1v in case of an undervoltage reset condit ion reset output ?ro? is held ?low? for v q 1 v, even if the input ?i? is not supplied and the voltage v i drops below 1 v. this is achieved by su pplying the reset circuit from the output capacitor. reset adjust function the undervoltage reset switching threshold can be adjuste d according to the application?s needs by connecting an external voltage divider ( r adj1 , r adj2 ) at pin ?radj?. for selecting the default threshold connect pin ?radj? to gnd. the reset adjustment range for the TLS820D0elv50 is given in reset threshold adjustment range . the reset adjustment range for the TLS820D0elv33 is given in reset threshold adjustment range . when dimensioning the volta ge divider, take into consid eration that there will be an additional current constantly flowing through the resistors. with a voltage divider connected, the reset switching threshold v rt,new is calculated as follows (neglecting the reset adjust pin current i radj ): v rt,lo,new = v radj,th ( r adj,1 + r adj,2 )/ r adj,2 (1) with ? v rt,lo,new : desired undervoltage reset switching threshold. ? r adj,1 , r adj,2 : resistors of the extern al voltage divider, see figure 6 . ? v radj,th : reset adjust switching threshold given in reset adjustment switching threshold . data sheet 22 rev. 1.0, 2016-02-08 TLS820D0 block description and electrical characteristics figure 7 typical timing diagram reset v i t v q t v rt , low v rt,hi gh v ro t v ro , low 1 v 1v t rr,int t rd thermal shutdown input voltage dip t rr,int t rd t rd t < t rr,blank under- voltage spike at output over - load v rh t rr,int t rd TLS820D0 block description and electrical characteristics data sheet 23 rev. 1.0, 2016-02-08 table 9 electrical characteristics reset t j = -40 c to +150 c, v i = 13.5 v, all voltages with respect to ground (unless otherwise specified) typical values are given at t j = 25 c parameter symbol values unit note / test condition number min. typ. max. output undervoltage reset 5v version only output undervoltage reset upper switching threshold v rt,high 4.6 4.7 4.8 v v q increasing p_5.7.1 output undervoltage reset lower switching threshold - default v rt,low 4.5 4.6 4.7 v v q decreasing radj = gnd p_5.7.2 output undervoltage reset switching hysteresis v rt,hy 60 100 ? mv radj connected to gnd p_5.7.3 output undervoltage reset headroom v q - v rt v rh 200 400 ? mv radj = gnd p_5.7.4 output undervoltage reset 3v3 version only output undervoltage reset upper switching threshold v rt,high 3.08 3.15 3.22 v v q increasing p_5.7.5 output undervoltage reset lower switching threshold - default v rt,low 3.0 3.05 3.13 v v q decreasing radj = gnd p_5.7.6 output undervoltage reset switching hysteresis v rt,hy 60 100 ? mv radj connected to gnd p_5.7.7 output undervoltage reset headroom v q - v rt v rh 100 250 ? mv radj = gnd p_5.7.8 reset threshold adjustment reset adjustment switching threshold v radj,th 1.15 1.20 1.25 v ? p_5.7.9 reset threshold adjustment range v rt,range 2.5 ? 4.4 v for v q,nom =5v p_5.7.10 reset threshold adjustment range v rt,range 2.5 ? 2.9 v for v q,nom =3.3v p_5.7.11 reset output ro reset output low voltage v ro,low ?0.20.4v1v v q v rt ; r ro 5.1 k ? p_5.7.12 reset output internal pull-up resistor r ro,int 13 20 36 k ? internally connected to q p_5.7.13 reset output external pull-up resistor to v q r ro,ext 5.1 ? ? k ? 1v v q v rt ; v ro 0.4 v p_5.7.14 reset delay timing reset delay time t rd,slow 13.2 16.5 19.8 ms dt connected to gnd p_5.7.20 reset delay time t rd,fast 6.8 8.5 10.2 ms dt connected to q p_5.7.21 reset blanking time t rr,blank ?6? s 1) for v q,nom =3.3v p_5.7.22 reset blanking time t rr,blank ?7? s 2) for v q,nom =5v p_5.7.46 internal reset reaction time t rr,int ?720sfor v q,nom =3.3v p_5.7.23 internal reset reaction time t rr,int ?1033sfor v q,nom =5v p_5.7.36 reset delay input dt delay input dt high signal valid v dt,h 2.0 ? ? v ? p_5.7.29 data sheet 24 rev. 1.0, 2016-02-08 TLS820D0 block description and electrical characteristics delay input dt low signal valid v dt,l ? ? 0.80 v p_5.7.30 delay input dt signal slew rate d v dt /d t 1?? v/s v dt,l data sheet 26 rev. 1.0, 2016-02-08 TLS820D0 application information 6 application information 6.1 application diagram note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 8 application diagram note: this is a very simplified example of an application ci rcuit. the function must be verified in the real application. 6.2 selection of external components 6.2.1 input pin the typical input circuitry for a linear voltage regulator is shown in the application diagram above. a ceramic capacitor at the input, in the range of 100 nf to 470 nf, is recommended to filter out the high frequency disturbances imposed by the line e.g. iso pulses 3a/b. this capacitor must be placed very close to the input pin of the linear voltage regulator on the pcb. an aluminum electrolytic capacitor in the range of 10 f to 470 f is recommended as an input buffer to smooth out high energy pulses, such as iso pulse 2a. this capaci tor should be placed close to the input pin of the linear voltage regulator on the pcb. an overvoltage suppressor diode can be used to furthe r suppress any high voltag e beyond the maximum rating of the linear voltage regulator and protect th e device against any damage due to over-voltage. the external components at the input are not mandatory for the operation of the voltage regulator, but they are recommended in case of possible external disturbances. 6.2.2 output pin an output capacitor is mandatory for th e stability of linear voltage regulators. the requirement to the output capacitor is given in ?functional range? on page 8 . the graph ?output capacitor series resistor esr(cq) versus output current iq? on page 15 shows the stable operation range of the device. c q load e. g. micro controller xc22 xx gnd regulated output voltage supply 100nf 47 f c i1 c i2 <45v d i2 1f d i1 r 1 r 2 bandgap reference gnd q i temperature shutdown en enable reset ro radj dt current limitation e .g. ignition TLS820D0 application information data sheet 27 rev. 1.0, 2016-02-08 TLS820D0 is designed to be also stable with low esr ca pacitors. according to the automotive requirements, ceramic capacitors with x5r or x7r dielectrics are recommended. the output capacitor should be placed as close as possible to the regulat or?s output and gnd pins and on the same side of the pcb as the regulator itself. in case of rapid transients of input voltage or load curr ent, the capacitance should be dimensioned in accordance and verified in the re al application that t he output stability requ irements are fulfilled. 6.3 thermal considerations knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation can be calculated: p d =( v i - v q ) i q + v i i q (2) with ? p d : continuous power dissipation ? v i : input voltage ? v q : output voltage ? i q : output current ? i q : quiescent current the maximum acceptable thermal resistance r thja can then be calculated: r thja,max =( t j,max - t a )/ p d (3) with ? t j,max : maximum allowed junction temperature ? t a : ambient temperature based on the above calculation the proper pcb type and the necessary heat sink area can be determined with reference to the specification in ?thermal resistance? on page 9 . example application conditions: v i = 13.5 v v q = 5 v i q = 150 ma t a = 85 c calculation of r thja,max : p d =( v i ? v q ) i q + v i i q ( v i i q can be neglected because of very low i q ) =(13.5v?5v)150ma =1.275w r thja,max =( t j,max ? t a )/ p d = (150 c ? 85 c) / 1.275 w = 50.98 k/w data sheet 28 rev. 1.0, 2016-02-08 TLS820D0 application information as a result, the pcb design must ensure a ther mal resistance r thja lower than 50.98 k /w. according to ?thermal resistance? on page 9 , at least 600 mm 2 heatsink area is needed on the fr4 1s0p pcb, or the fr4 2s2p board can be used to ensure a proper cooling for the TLS820D0 in pg-ssop-14 package. 6.4 reverse polarity protection TLS820D0 is not self protected against reverse polarity faults and must be protec ted by external components against negative supply voltage. an external reverse polarity diode is ne eded. the absolute maximum ratings of the device as specified in ?absolute maximum ratings? on page 7 must be kept. 6.5 further application information ? for further information you may contact http://www.infineon.com/ TLS820D0 package outlines data sheet 29 rev. 1.0, 2016-02-08 7 package outlines figure 9 pg-ssop-14 green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). pg- ss op-14 1 7 14 8 14 17 8 14x 0.25 0.05 0.05 2) m 0.15 d c a-b 0.65 c s tand off 0.05 (1.45) 1.7 max. 0.0 8 c a b 4.9 0.1 1) a-b h 0.1 2x 1) doe s not incl u de pl as tic or met a l protr us ion of 0.15 m a x. per s ide 2) le a d width c a n b e 0.61 m a x. in d a m ba r a re a bottom view 0.2 3 0.2 2.65 0.2 d h 6 14x 0.64 0.25 3 .9 0.1 1) 0. 3 5 x 45 0.1 hd 2x 0.2 c +0.06 0.19 8 max. index m a rking expo s ed diep a d s eating plane 6 x 0.65 = 3 .9 for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm data sheet 30 rev. 1.0, 2016-02-08 TLS820D0 revision history 8 revision history revision date changes 1.0 2016-02-08 data sheet - initial version trademarks of infineon technologies ag aurix?, c166?, canpak?, cipos?, cipurse?, coolmos?, coolset?, core control?, crossave?, dave?, di-pol?, easypim?, econobridge?, econodual?, econopim?, econopack?, eicedriver?, eupec?, fcos?, hi tfet?, hybridpack?, i2rf?, isof ace?, isopack?, litix?, mipaq?, modstack?, my-d?, novalithic?, optimos?, origa?, powercode?, pr imarion?, primepack?, primestack ?, pro-sil?, profet?, rasic?, reversave?, satric?, sieget?, sindrion?, sipmos?, smartlewis?, spoc?, solid flash?, tempfet?, th inq!?, trenchstop?, tricore?. other trademarks advance design system? (ads) of agilent tech nologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? o f arm limited, uk. autosar? is licensed by autosar developm ent partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvco, llc (visa holdings inc.). epcos? of epcos ag. flexgo? of microsoft corporation. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of co mmission electrotechnique internationale. irda? of infrared dat a association corporation. iso? of international organiza tion for standardization. matlab? of mathwo rks, inc. maxim? of maxim integrated prod ucts, inc. microtec?, nucleus? of mentor graphics corporation. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwav e office? (mwo) of applied wave research inc., om nivision? of omnivision te chnologies, inc. openwave ? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius satellite radio inc. solaris? of sun microsy stems, inc. spansion? of spansion llc ltd. symbian? of symbian softwa re limited. taiyo yuden? of taiyo yuden co . teaklite? of ceva, inc. tektronix? of t ektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladi um? of cadence design systems, inc. vlynq? of texas instruments incorporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex limited. last trademarks update 2011-11-11 edition 2016-02-08 published by infineon technologies ag 81726 munich, germany ? 2016 infineon technologies ag. all rights reserved. do you have a question about any aspect of this document? email: erratum@infineon.com legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non- infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.infineon.com |
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